Multi-layer three-dimensional (3D) integrated memory devices have been recently proposed as a way to achieve high density storage in a relatively small footprint. Such devices can be formed by stacking separate layers of memory cells in a vertical direction to integrate the memory cells into a single memory space.
While operable, a limitation with such multi-layer memory devices relates to overall process yields in terms of the percentage of non-defective chips in a given manufacturing process. The overall yield can generally be determined by multiplying the yield percentage of each layer in the stack. The compound chip yield in a given process may tend to decrease significantly as the number of stacked layers increase. Factors that can negatively impact process yield include defects in a single layer, misalignments between adjacent layers, and mechanical defects incurred during the attachment process.
Redundant cells (spares) are often utilized to address defects at the layer level. When one or more defective cells (bits) in a layer are identified during testing, a memory decoder can deallocate the defective bits and allocate new replacement bits from the redundant cell pool on that layer.
Defects in multi-layer memory devices may have a significant “localization effect.” If a particular layer has a relatively high defect rate (e.g., high number of defective cells), it is likely that the redundant cells on the layer may also have a relatively large number of defects. Providing sufficient redundant cells to handle the worst-case defect rates on each layer may reduce the overall data capacity of the array, and may unnecessarily limit overall storage capacity since some layers may have relatively few defects. Nevertheless, in the past an entire layer, or even an entire multi-layer chip, may have been discarded from the manufacturing process because a single layer within the chip had too many defects to be accommodated by the available spare cells on that layer.